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TA1322FN
Preliminary
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1322FN
Down-Converter IC with PLL for Satellite Tuner
The TA1322FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL. The I2C bus data format is used as the data control format. The supply voltage of 5.0 V helps minimize the tuner's power dissipation, while the compact 30-pin SSOP package allows the tuner to be kept small.
Features
* * * * * * * * * * * * * * * Supply voltage: 5.0 V (typ.) Wide input frequency range Low phase noise oscillator Standard I2C bus format control 4-MHz (X'tal) buffer output pin Reference oscillator input change-over switch [X'tal or external input] 33-V high-voltage tuning amplifier built-in Built-in comparator (P4, P5, P7) Bandswitch drive transistor (P0) [IBD = 40 mA (max)] Selected IF output port Frequency step: 62.5 kHz or 125 kHz (for 4-MHz X'tal) 4-address setting via address selector Power-on reset circuit x1/2 prescaler Flat compact package: SSOP30-P-300-0.65 (0.65-mm pitch) Weight: 0.17 g (typ.)
Power-On Reset Operation Conditions
* * * * * * Frequency step: 125 kHz Charge pump output current: 50 A Counter data: all [0] Band driver: OFF Tuning amplifier: OFF IF output operation: pin 19 is ON Note 1: This device can easily be damaged by high voltages or electrical fields. For this reason, please handle it with care.
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TA1322FN
Block Diagram
SDA in/out 16 15 SCL in
ADR set
XO SW
30
29
28
27
26
25
24
23
22
21
20
19
18
17
XO-SW IF-SW
Address
Band Driver
2
Programmable Counter 1/2 1/32 1/33 Divider
I C BUS Data Interface
Phase Comparator
Comparator
1 GND1
2 VCC1
3 OSC-E
4 OSC-B
5 GND2
6 Vt-out
7 NF
8 X'tal
9 VCC2
10 XO buff out
11 GND3
12 P4
13 P5
14 P7
2
PO out
IF out2
IF out1
RF in2
RF in1
GND7
GND6
GND5
GND4
TEST
VCC4
VCC3
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TA1322FN
Pin Functions
Pin No. 1 2 Pin Name GND1 VCC1 Function Ground pin for oscillator circuit block Power supply pin for local oscillator circuit block 2 Interface 3/4
3 Oscillator 4 Local oscillator circuit
4 3
GND1 5 GND2 Ground pin for oscillator circuit block VCC2 6 Vt Output 6 Tuning voltage output pin with built-in tuning amplifier GND3 7 NF 7 VCC2 VCC2 1 kW 5 kW 5 kW 5 kW 5 kW 50 W 3/4
Crystal oscillator input Reference Input 8 (4-MHz input) Can be switched between X'tal oscillator and external input using pin 24 (XO switch).
8
1 kW
GND3 9 VCC2 Power supply pin for PLL circuit block VCC2 3/4
10
Reference signal buffer output
Buffer output pin for reference signal
10
GND3 11 GND3 Ground pin for PLL circuit block 3/4
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Pin No. Pin Name Function Interface
12
P4
Output can be controlled by setting the band switch data. The circuit configuration is open collector output. Each pin has a built-in comparator. The status of the comparator can be checked READ mode.
CMOP 12, 13, 14
13
P5
GND3
14
P7
VCC2
15
SCL Input
Input pin for I C bus serial clock data
2
15
1 kW 100 W
GND3
VCC2
SDA 16 Input/Output
Input/output pin for I C bus serial clock data
2
16
20 W
1 kW 100 W 100 W 12 kW
GND3
17
PO output
Output can be controlled by setting band switch data. 17
DATA I/F
GND3
VCC2 150 kW 18 100 W 1 kW 50 kW GND3
18
ADR Set
The address for hardware bit setting can be selected by applying voltage to this pin. 4 programmable address can be programmed.
12 kW
VCC2
70 kW
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Pin No. Pin Name IF output pin. 19 IF Output 1 Output can be controlled by setting the band switch data (P6). IF output impedance is 75 W each other. When P6 data set 0, output pin is Pin 19 (IF output 1). When P6 data set 1, output pin is Pin 21 (IF output 2). 20 22 23 GND4 VCC3 GND5 Ground pin for IF amplifier circuit block Power supply pin for IF amplifier circuit block Ground pin for IF amplifier circuit block VCC2 25 kW Determines reference signal input. 24 XO Switch If connected to ground: X'tal oscillator. If open or connected to VCC2: external input GND3 24 1 kW 3/4 3/4 3/4 GND4, 5 19, 21 Function Interface VCC3
21
IF Output 2
VCC2
25
TEST
This pin can be used at open.
GND3 3/4
26
GND6
Ground pin for mixer circuit block
27
RF Input1 RF signal input pin Input can be either balanced or unbalanced.
27 3 kW 3 kW
100 kW
When test mode set, this pin can confirm X'tal divider signal and 1/2 counter signal.
25 kW
25
25 kW 28
28
RF Input2 GND7
29 30
GND7 VCC4
Ground pin for mixer circuit block Power supply pin for mixer circuit block
3/4 3/4
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Absolute Maximum Ratings (Ta = 25C)
Parameter Pin No. 2 Supply voltage 9 22 30 Tuning amplifier voltage Power dissipation Operating temperature Storage temperature 6 3/4 3/4 3/4 Symbol VCC1 VCC2 VCC3 VCC4 VBT PD Topr Tstg Rating 6 6 6 6 38 1130 mW (Note 2) -20 to 85 -55 to 150 C C V V Unit
Note 2: 50 mm 50 mm 1.6 mm, 40% Cu board If Ta > 25C, derate this value by 9.1 mW/C.
Recommended Operating Conditions
Pin No. 2 9 22 30 Symbol Local oscillator block PLL block IF amplifier block Mixer block VCC1 VCC2 VCC3 VCC4 Min 4.5 4.5 4.5 4.5 Typ. 5.0 5.0 5.0 5.0 Max 5.5 5.5 5.5 5.5 Unit V V V V
Electrical Characteristics
DC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C) When power on, counter data = all [0], VBT = OFF, CP0 = 0, band = all [0], and IF output operate Pin 19.
Parameter Symbol ICC1 Power supply current ICC2 ICC3 ICC4 Total ICC-total 3/4 1 Test Circuit Test Condition 3/4 3/4 3/4 3/4 3/4 Min 5.0 21.5 19.5 10.0 56.0 Typ. 7.5 26.5 24.0 12.5 70.0 Max 9.5 32.0 29.0 15.5 86.0 mA mA Unit
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Down-Converter Block
AC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C)
Parameter RF input frequency RF input level IF output frequency IF output impedance Local oscillator frequency Conversion gain CG (Note 3) 3 (Note 3) Symbol Mfin MPin Afin AZout LO Test Circuit 3/4 3/4 3/4 3/4 3/4 Single-end 3/4 fRF = 898 MHz fRF = 1598 MHz fRF = 2198 MHz fRF = 898 MHz NF (Note 3) 4 fRF = 1598 MHz fRF = 2198 MHz fRF = 898 MHz Apsat (Note 3) 3 fRF = 1598 MHz fRF = 2198 MHz fd = 898 MHz, fud = 903 MHz IP3 (Note 3) 5 fd = 1598 MHz, fud = 1603 MHz fd = 2198 MHz, fud = 2203 MHz fRF = 898 MHz CGs (Note 3) 3 fRF = 1598 MHz fRF = 2198 MHz fosc = 1300 MHz DfB 3 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz PN (with 10-kHz offset) 3 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz LORF LO leak level 3 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz LOIF LO leak level 3 fosc = 2000 MHz fosc = 2600 MHz fRF = 898 MHz IF switch isolation IFiso 3 fRF = 1598 MHz fRF = 2198 MHz Test Condition (Note 4, Note 5) 3/4 3/4 3/4 Min 850 3/4 350 3/4 1300 27.5 27 24.5 3/4 3/4 3/4 6 6 6 13 14 14 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 30 30 30 Typ. 3/4 3/4 3/4 75 3/4 30.5 31 29 9 9 11 8 8 8 15 16 16 3/4 3/4 3/4 3/4 3/4 3/4 -74 -75 -74 -36 -31.5 -33 -21.5 -31 -36 36 36 36 Max 2200 -35 550 3/4 2700 33.5 34 32 10.5 11.5 13 3/4 3/4 3/4 3/4 3/4 3/4 2 2 2 5.5 3.5 3.5 -70 -71 -70 -33 -28 -30 -15.5 -25 -30.5 3/4 3/4 3/4 dB dBmW dBmW dBc/ Hz MHz dB dBmW dBmW dB dB Unit MHz dBmW MHz W MHz
Noise figure
IF output power level
3rd inter modulation (IF output intercept point)
Conversion gain shift
Frequency shift (PLL OFF)
Phase noise
RF pin
IF pin
Note 3: IF output frequency = 402 MHz Note 4: IF output load = 75 W Note 5: IF output operate Pin 21
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PLL Block (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C)
Parameter Tuning amplifier output voltage (close) Tuning amplifier maximum current X'tal negative resistance X'tal operating frequency X'tal external input level X'tal external input frequency Ratio setting range Logic input low voltage Logic input high voltage Logic input current (low) Logic input current (high) ACK output voltage Charge pump output current Band driver drive current Band driver voltage drop Comparator pin input voltage Comparator pin low voltage Comparator pin high voltage Output port flow current Output port saturation voltage Output port leakage current Output port maximum voltage Symbol Vt out Ivt XtR OSCin Xo extl X-ext N VIL VIH I BsL I BsH VACK Ichg IBD VBDsat VCMP VLCMP VHCMP IPin Vpinsat Iplk Vport Test Circuit 1 1 1 1 1 1 3/4 1 SDA and SCL pins 1 1 SDA and SCL pins 1 1 1 1 1 1 1 1 2 2 1 1 ISINK = 3 mA CP = [0] CP = [1] P0 P0: IBD = 40-mA drive IP4, IP5, IP7 IP4, IP5, IP7 IP4, IP5, IP7 P4, P5, P7 P4, P5, P7 (Ipin = 7 mA) P4, P5, P7 (Vport = 6 V) P4, P5, P7 1-kW, 10-pF load X'tal: NDK (AT-51), 4 MHz used. 4-MHz level monitored on oscilloscope using FET probe (1 MW, 1.9 pF). 3/4 3 -20 -10 3/4 35 180 3/4 3/4 0 0 2.7 3/4 3/4 3/4 3/4 XO-SW: VCC2 or open 15-bit counter Test Condition VBT = 33 V, RL = 33 kW VBT = 33 V XO-SW:GND (X'tal oscillator mode) [NDK (AT-51), 4 MHz used] Min 0.3 3/4 1 3.2 100 2 1024 -0.3 Typ. 3/4 3/4 2.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50 240 3/4 0.2 3/4 3/4 3/4 3/4 0.1 3/4 3/4 Max 33 3 3/4 4.5 1000 6 32767 1.5 VCC2 + 0.3 10 20 0.4 75 345 40 0.4 6 1.5 6 7 0.15 10 6 V V mA mA V mA mA V V V V mA V mA V Unit V mA kW MHz mVp-p MHz
Xo buffer output level
Xo out
1
350
500
mVp-p
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Bus Line Characteristics
Parameter SCL clock frequency Bus free time between a STOP and START conditions Hold time for repeated START condition SCL clock low period SCL clock high period Set-up time for repeated START condition Data hold time Data set-up time Rise time for SDA and SCL signals Fall time for SDA and SCL signals Set-up time for STOP condition Symbol fSCL tBUF tHD; STA tLOW tHIGH fSU; STA tHD; DAT tSU; DAT tR tF tsU; STO 3/4 Please refer to data timing chart. Test Circuit Test Condition Min 0 4.7 4 4.7 4 4.7 0 250 3/4 3/4 4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 100 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1000 300 3/4 Unit kHz ms ms ms ms ms ms ns ns ns ms
SDA tBUF
tLOW SCL
tR
tF
tHD; STA
tHD; STA P S
tHD; DAT
tHIGH
tSU; DAT tSU; STA Sr
tSU; STO P
Figure 1
I C Bus Data Timing Chart (rising-edge timing)
2
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Test Conditions
(1) Conversion gain RF input level = -40dBmW Noise figure NF meter direct-reading value (DSB measurement) IF output power level Measure maximum IF output level. 3rd inter modulation * fd (fd input level = -40dBmW) * fud = fd + 5 MHz (fud input level = -40dBmW) Calculate IF output intercept point as follows: IP3 = S/(N - 1) + P [dBmW] S: suppression level N: 3 P: IF output level Conversion gain shift Conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges VCC = 5 V to 4.5 V or VCC = 5 V to 5.5 V. Frequency shift (PLL OFF) Frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges VCC1 = 5 V to 4.5 V or VCC1 = 5 V to 5.5 V. Phase noise (offset = 10 kHz) Measure phase noise at 10-kHz offset. RF pin local-leak level Measure worst-case local-leak level for RF pin (with IF output pin open). IF pin local-leak level Measure worst-case local-leak level for IF pin (with RF input pins shorted using 50-W resistor, and not measure IF output pin open).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) IF switch isolation RF input level = -40dBmW Measure selected IF output pin's level, and not selected IF output pin's level. Ifiso = |(selected IF output pin's level ) - (not selected IF output pin's level)| Not selected IF output pin shorts using 50 W resistor.
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PLL Block --I C Bus Communications Control-The TA1322FN conforms to Standard Mode I2C bus format. I2C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for processing status data). Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte. If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected. Address can be set using the hardware bits. 4 programmable address can be programmed. Using this setting, multiple frequency synthesizers can be used on the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin 18). The address is selected according to the setting of these bits. During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low. If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low during the next acknowledgment. A) Write mode (setting command) When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte 4 holds the divider ratio setting and function setting data; and byte 5 holds output port data. Data is latched and transferred at the end of byte 3, byte 4 and byte 5. Byte 2 and byte 3 are latched and transferred as a byte pair. Once a valid address has been received and acknowledged, the data type can be determined by reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1, the data is function-setting or band output data. Additional data can be input without the need to transmit the address data again until the I2C bus STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible). If a data transmission is aborted, data programmed before the abort remains valid. [[BYTE 1]] The address data for byte 1 can be set using the hardware bit. The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 18). [[BYTE 2, BYTE 3]] Byte 2, byte 3 control the 15-bit programmable counter ratio and are stored in the 15-bit shift register together with frequency setting counter data. The program frequency can be calculated using the following formula: fosc = 2 fr N fosc: Program frequency fr: Phase comparator reference frequency N: Counter total divider ratio
2
fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (the control byte). (fr = X'tal oscillator frequency/reference divider ratio) The reference frequency divider ratio can be set to 1/64 or 1/128. When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step frequencies are 125 kHz and 62.5 kHz. [[BYTE 4]] Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the charge-pump circuit. When bit 2 is set to [0], the output current is set to 50 mA; when set to [1], 240 mA. Bit 3 (T1) is used to set the test mode. When bit 3 is set to [0], normal mode; when set to [1], test mode. Bit 4 (T0) is used to set the charge pump. When bit 4 is set to [0], charge pump is ON (normal used); When set to [1], charge pump is OFF. Bit 5 (TS2) and bit 6 (TS1) used to set the test mode. They are used to set the charge pump test, phase comparator reference signal output, and 1/2 counter divider ratios. Bit 7 (TS0) is used to set the X'tal reference frequency divider ratio. When bit 7 is set to [0], 1/128 (frequency step is 62.5 kHz); when set to [1], 1/64 (frequency step is 125 kHz). Bit 8 (OS) is used to set the charge pump drive amplifier output setting. When bit 8 is set to [0],
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the output is ON (normal mode); when set to [1], the output is OFF. [[BYTE 5]] Byte 5 can be used to set control the output port. Bit 1 (P7), bit 3 (P5) and bit 4 (P4) are used to control output port P7, P5 and P4. Bit 2 (P6) is used to control change IF output port. When bit 2 is set to [0], IF output 1 (pin 19) is ON; when set to [1], IF output 1 (pin 21) is ON. Bit 8 (P0) is used to control band output port (P0). When bit 8 is set to [0], P0 is OFF; when set to [1], P0 is ON. (P0) output port can be driven at less than 40 mA. B) READ mode (status request) When READ mode is set, power-on reset operation status, phase comparator lock detector output status, comparator input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC2 stops, bit is set to [1]. The condition for reset to [0], voltage supplied to VCC2 is 3 V or higher, transmission is requested in READ mode, and the status is output. (when VCC2 is turned on, bit 1 is also set to [1].) Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output; when unlocked, [0] is output. Bit 3 (IP7), bit 4 (IP5) and bit 5 (IP4) indicate the input comparator status. High level status is output [1], low level status is output is [0]. When voltage applied from 0 V to 1.5 V, output is [0]. When from 2.7 V to 6 V, output is [1].
Data Format
A) Write mode
MSB 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte Band SW Byte 1 0 N7 1 P7 1 N14 N6 CP P6 0 N13 N5 T1 P5 0 N12 N4 T0 P4 0 N11 N3 TS2 MA1 N10 N2 TS1 MA0 N9 N1 TS0 LSB R/W = 0 N8 N0 OS P0 ACK ACK ACK (L) ACK (L) ACK (L)
: Don't care ACK: Acknowledged (L): Latch and transfer timing B) Read mode
MSB 1 2 Address Byte Status Byte 1 POR 1 FL 0 IP7 0 IP5 0 IP4 MA1 1 MA0 1 LSB R/W = 1 1 ACK 3/4
ACK: Acknowledged
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Data Specifications
* MA1 and MA0: programmable hardware address bits
MA1 0 0 1 1 MA0 0 1 0 1 Voltage Applied to Address Pin 0 to 0.1VCC2 OPEN or 0 to VCC2 0.4VCC2 to 0.6VCC2 0.9VCC2 to VCC2
* *
N14-N0: programmable counter data CP: charge pump output current setting [0]: 50 mA (typ.) [1]: 240 mA (typ.)
*
T1: test mode setting [0]: normal mode [1]: test mode
*
T0: charge pump setting [0]: charge pump is ON (normal mode) [1]: charge pump is OFF
*
TS0: X'tal reference frequency divider ratio select bits.
TS0 0 1 Divider ratio 1/128 1/64 Step frequency 62.5 kHz 125 kHz fr 31.25 kHz 62.5 kHz
*
T1, TS2, TS1, TS0: test mode
Characteristics Normal operation Normal operation Sink Charge pump Source Output port OFF Phase comparator test 1 1 1 1 X'tal divider counter output 1 1 1/2 counter divider output 1 0 1 1 1/64 0 0 0 1 1 0 1/64 1/128 Output to pin 25 (TEST) 0 1 1 1 1 0 1 0 1/64 SCL: Reference signal input 1/128 Output to pin 25 (TEST) 0 1 1 0 1/64 1/128 P7, P5, P4 OFF SDA: Comparative signal input T1 0 0 1 TS2 1 TS1 0 TS0 0 1 0 Divider ratio 1/128 1/64 1/128 Notes 3/4 3/4 3/4 3/4
: DON'T CARE Note 5: When test mode, OS = 0 (tuning ON) is necessary. When testing the counter divider output, programmable counter data input is necessary.
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* OS: tuning amplifier control setting [0]: Tuning amplifier ON (normal operation) [1]: Tuning amplifier OFF * P4, P5, P7: output port [0]: OFF [1]: ON * P6: IF output port switchover
P6 0 1 Output Port IF output 1 (pin 19) is ON IF output 2 (pin 21) is ON
*
P0: band output [0]: OFF [1]: ON This can be driven at less than 40 mA.
*
POR: power-on reset flag [0]: normal operation [1]: reset operation
*
FL: lock detect flag [0]: Unlocked [1]: Locked
*
IP4, IP5, IP7: comparator output [0]: supply voltage is from 0 V to 1.5 V [1]: supply voltage is from 2.7 V to 6 V
*
XO-SW: reference signal input changeover
Pin 24 GND VCC2 or open Input Method X'tal External input
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Test Circuit 1
DC Characteristics
VCC2/Open: Extenal input GND: X'tal
SDA IBD VCC3 (5 V) A V VBDsat ADR set A ICC3 0.01 mF 390 W 17 16 14 15 390 W P4 P5 P7 SCL
VCC2/Open VCC4 (5 V) TEST A ICC4 0.01 mF 1 nF 1 nF XO-SW
30
29
28
27
26
25
24 XO-SW
23
22
NC 21
20
NC 19
18 Address
IF-SW Band Driver
2
Programmable Counter 1/2 1/32 1/33 Divider
I C BUS Data Interface
Phase Comparator
Comparator
A ICC1 1 nF VCC1 (5 V) NF *X'tal 22 pF
A ICC2 10 pF 4 MHz out
EXT.in VCC2 (5 V)
X'tal: NDK (AT-51), 4 MHz
1 nF
NC
NC
NC
0.01 mF
1
2 0.01 mF
3
4
5
6
7
8
9
10
11
12
13
1 kW
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Test Circuit 2
DC Characteristics Measurement for "Output port flow current" and "Output port saturation voltage".
12, 13, 14
IPin
A
V VPinsat
Test Circuit 3
AC Characteristics
5V
VCC2/Open: Extenal input GND: X'tal
VCC2/Open RF in XO-SW 1 nF 1 nF 390 W 18 17 16 Address IF-SW Band Driver
2
IF out 2
IF out 1
ADR set
PO out
SDA
1 nF
0.1 mF
1 nF
30
29
28
27
26
TEST 25
24
23
22
0.1 mF
21
20
19
XO-SW
Programmable Counter 1/2 1/32 1/33 Divider
1 nF I C BUS Data Interface Comparator 11 12 13
Phase Comparator
47 pF
0.1 mF
1 0.1 mF
2 1T379
3
4 10 kW 4.7 kW 1T379 4.7 nF
5 5 pF
6
7
8 X'tal 22 pF
9
10 1 nF
14
15 390 W
4.7 nF
0.1 mF
L
13 kW
4 MHz out
P4
P5
P7
SCL
47 kW 33 V 1 nF
10 kW
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Test Circuit 4
Measuring Noise Figure
Noise Figure Meter
out
in
IF output pin 28 Noise source DUT 75 W-50 W impedance transformer
Test Circuit 5
Measuring 3rd Inter Modulation
fd Signal Generator 1 IF output pin 28 DUT 75 W-50 W impedance transformer in Spectrum Analyzer
Signal Generator 2 fud
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I C-Bus Control Summary
The bus control format of TA1322FN conforms to the Philips I2C-bus control format.
2
Data Transmission Format
S Slave address 7 bits MSB MSB 0A SUB address 8 bits MSB A Data 8 bits AP
S: Start condition P: Stop condition A: Acknowledge (1) Start/stop condition
Serial Data
Serial Clock S Start condition P Stop condition
(2)
Bit transfer
Serial Data
Serial Clock
Serial data unchanged.
Serial data can be changed.
(3)
Acknowledge
Serial Data From Master Device
High-Impedance
Serial Clock From Slave
High-Impedance
Serial Clock From Master Device S
1
8
9
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TA1322FN
(4) Slave address
A6 1 A5 1 A4 0 A3 0 A2 0 A1 * A0 * R/W 0
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Tights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Handling Precautions
1. The device should not be inserted into or removed from the test jig while a voltage is being applied to it: otherwise the device may be degraded or break down. Also, do not abruptly increase or decrease the power supply to the device (see figure 1). Overshoot or chattering in the power supply may cause the IC to be degraded. To avoid this, filters should be placed on the power supply line.
6 V (VCC1, VCC2, VCC3, VCC4) 38 V (VBT) Supply voltage
90%
10%
1 ms
Time
Figure 1
2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the device's performance. TOSHIBA intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, the mounting method and other factors relating to the application design. Therefore, the evaluation of the characteristics of application circuits is the responsibility of the designer. TOSHIBA only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer's application design. In order to better understand the quality and reliability of TOSHIBA semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (integrated circuits) published by TOSHIBA Semiconductor Company. This handbook can also be viewed on-line at the following URL: .
3.
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TA1322FN
Package Dimensions
Weight: 0.17 g (typ.)
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TA1322FN
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2002-02-12

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